The present invention relates to a nonvolatile semiconductor memory in which each of memory cells is made of an insulated gate transistor having a floating gates and stores multi-bits information of plural bits data.
A flash memory or another nonvolatile memory has a structure in which an MOS transistor usually provided with a floating gate constituting a charge storage layer and a control gate laminated therein forms one cell. By controlling a threshold of the transistor with a charge stored in the charge storage layer, data is stored. For a relationship between a type of data stored in one cell of a multi-valued memory and a number of thresholds, when two values are stored in one cell, two thresholds are controlled, while when n-values are stored in one cell, n-thresholds are controlled. In the same manner, when m-ary k-bits (an integer of m.gtoreq.2, an integer of k.gtoreq.2 (m=2), or an integer of k.gtoreq.1 (m.gtoreq.3)) are stored in one cell, m.sup.k thresholds need to be controlled.
Here, the charge stored in the charge storage layer of the memory cell varies with a leakage from the charge storage layer and a disturbance received when data is read from or written into another surrounding memory cell. In this case, there is a possibility that the threshold is changed and the data is destroyed. Especially, in the multi-valued memory in which a large number of thresholds need to be controlled, a margin for allowing a variation in threshold is reduced.
As one of methods for preventing an error caused by a variation of threshold, the variation of threshold is detected before the variation of threshold exceeds its tolerance, so that the memory cell is returned to its correct condition. Such prior art is proposed in a publication of the patent application laid-open No. 8-77785 which relates to a semiconductor memory device. In the following the prior art is described using drawings.
FIGS. 10 and 11 are explanatory views of a method of detecting a variation of threshold according to the prior art. FIG. 10 is a circuit diagram showing a constitution of the semiconductor memory device described in the aforementioned publication. FIG. 11 is a voltage distribution diagram showing a method of determining multiple values and a variation of threshold in FIG. 10, and shows a relationship between a threshold and a word line voltage when four values (binary two bits) are stored in a memory cell. In the following, the case four values are stored is described.
In the circuit diagram of FIG. 10, a constitution is provided with a memory cell 61, a load 62, an amplifier 63 for detecting a variation in level of a contact N6, a word line voltage generator 69 for generating a stepped word line voltage, an output circuit 65 for determining outputs o1, o2 from outputs of the word line voltage generator 69 and the amplifier 63 and emitting the outputs, a latch circuit 66 for latching the outputs o1, o2 and emitting outputs o1*, o2*, and a comparator 67 for comparing the outputs o1, o2 of the output circuit 65 with the outputs o1* and o2* of the latch circuit 66 and emitting a threshold voltage variation signal s when a variation in threshold voltage is detected. The memory cell 61 and the load 62 constitute a bit line. Detailed structure is not an essential portion in the invention, therefore its description is omitted.
In FIG. 11, initial distributions A, B, C and D of thresholds in the contact NE when data is read from the memory cell correspond to stored data "11", "10", "01" and "00", respectively. Word line voltages Vwa, Vwb, Vwc are applied to a control gate of the memory cell 61. In the prior art, reading is performed while gradually increasing the word line voltage to Vwa, Vwb, then Vwc sequentially.
Here, when the threshold is in a position b, no current flows in the memory cell at the word line voltage of Vwa. However, when the voltage increases to Vwb, a current flows. Specifically, the cell turns on at Vwa and off at Vwb and Vwc. Then, it can be determined that the threshold is in the position b, i.e. within a range of B (data "10").
However, when the threshold, which has been at the position b (Vwa.ltoreq.b.ltoreq.Vwb) at the time of writing, varies exceeding a range of Vwa and Vwb, the threshold is determined as another value, thereby causing an error. To avoid the error, a threshold verifying means is applied in which a cell with a threshold varying but within a tolerance is found and repaired. In the prior art shown in FIG. 11, word line voltages VwaH, VwbH, VwcH and word line voltages VwaL, VwbL, VwcL are used as the threshold verifying means.
Here, when data "10" is stored, the threshold is in the position b. In this case, for a verifying process, reading is first performed at the usual word line voltages Vwa, Vwb and Vwc, the data is determined to be "10", and is then latched in the latch circuit 66.
Subsequently, at the word line voltages VwaH, VwbH, VwcH, reading is performed. Here, as shown in FIG. 11, when the threshold varies from the position b to b1, the memory cell turns on at all the voltages VwaH, VwbH, VwcH, then the data is determined to be "11", which is compared by the comparator 67 with the latched data "10". As a result, they do not coincide with each other, and the variation in threshold voltage can be detected. Subsequently, a threshold voltage variation signal s indicating that the variation in threshold voltage is detected is emitted from the comparator 67. After the variation in threshold is detected, a rewriting operation is performed, so that the threshold again falls within the range B. Since the rewriting operation is not handled in the invention, its description is omitted.
When, at the time of reading at the word line voltages VwaH, VwbH, VwcH, no variation in threshold is detected, the data "10" latched in the latch circuit 66 is not canceled, then reading is performed at the word line voltages VwaL, VwbL, VwcL. Here, as shown in FIG. 11, when the threshold varies from the position b to b2, the memory cell turns off at VwaL, VwbL and turns on at VwcL, then the data is determined to be "01", which is compared by the comparator 67 with the latched data "10". As a result, they do not coincide with each other, and the variation in threshold voltage can also be detected. Subsequently, the threshold voltage variation signal s indicating that the variation in threshold voltage is detected is emitted from the comparator 67. After the variation in threshold is detected, the rewriting operation is performed, so that the threshold again falls within the range B.
If at the time of detection both at the word line voltages VwaH, VwbH, VwcH and the word line voltages VwaL, VwbL, VwcL, the threshold voltage variation signal s is not emitted (for example, when the threshold is in a position b#), then it is determined there is no variation in threshold voltage.
In this manner, by using nine types of word line voltages, the variation in threshold and a direction of the variation can be detected. Also, in the prior art, no determination is made when the threshold of the memory cell becomes negative or higher than D. However, by increasing the types of word line voltages, the determination can be made.
In the aforementioned prior art, for reading out one data, three types of word line voltages need to be changed. Therefore, problem is a low reading speed. Also, the voltage needs to be changed over eight times at maximum. The word line voltage needs to be fixed until the output of the amplifier is stabilized and a comparison result is attained. There is a problem that a long time is required for the verifying process. Further, for the verifying process, nine types of word line voltages in total are necessary. Therefore, another problem is that a structure of the word line voltage generator is complicated.